Simultaneous Signature and Syndrome Compression

An important organization for built-in self-test of VLSI circuits uses complete or psuedorandom test input generators followed by output data reduction. Two compression techniques which have been used are polynomial division (signature) and ones counting (syndrome). The simultaneous use of both of these approaches in parallel is investigated. Analytic and enumerative results indicate that the number of error patterns which are missed by both methods is nearly the theoretical minimum. The conclusion extends to signature compression combined with any other counter-based compression method such as Walsh spectral coefficients. Some suggestions for CAD implemented test design are given based on these results.